SPT1175 8-bit, 20 msps cmos a/d converter signal processing technologies, inc. 4755 forge road, colorado springs, colorado 80907, usa phone: (719) 528-2300 fax: (719) 528-2370 features ? 20 msps maximum conversion rate ? internal sample-and-hold function ? 90 mw power dissipation ? internal voltage reference ? single +5.0 v power supply ? three-state ttl-outputs ? cmos compatible clock applications ? video digitizing ? image scanners ? personal computer video ? medical ultrasound ? multimedia ? digital television data latches and 3-state output buffer error correction circuit latch coarse sampling amplifier reference matrix timing generator latch analog mux fine sampling amplifier fine sampling amplifier encoder encoder dgnd dv dd v rbs v rb v in v rt v rts agnd av d dv dd agnd d (lsb) d1 d2 d3 d4 d5 d6 d7 (msb) clk oe general description the SPT1175 is a cmos two-step a/d converter capable of digitizing full scale analog input signals into 8-bit digital words at a sample rate of 20 msps. for most applications, no external sample-and-hold or video driving amplifiers are required due to the device's narrow aperture time, wide bandwidth, and low input ca- pacitance. the SPT1175 operates from a single +5.0 v power supply and has an internal voltage reference which eliminates the need for external reference circuitry. all digital inputs are cmos compatible and the tri-state outputs are ttl-compat- ible. the SPT1175 is ideal for most video and image pro- cessing applications that require low power dissipation and low cost. the SPT1175 is available in 24-lead plastic soic, plastic dip, and plcc packages over the commercial tem- perature range (0 to +70 c). it is also available in die form. block diagram
spt 2 6/24/97 SPT1175 electrical specifications t a = +25 c, av dd =dv dd =+5.0 v, agnd=dgnd=0.0 v, v rb =+0.6 v and v rt =+2.6 v, unless otherwise specified. test test SPT1175 parameters conditions level min typ max units resolution 8 bits dc accuracy (+25 c) integral nonlinearity i 0.8 1.2 lsb differential nonlinearity i 0.6 1.0 lsb no missing codes i guaranteed analog input input voltage range i v rb v rt v input bias current i 5.0 m a input resistance vi 100 200 k w input capacitance v 15 pf input bandwidth v 12 mhz reference input reference ladder resistance i 200 300 400 w reference current i 5.0 6.7 10.0 ma reference input voltage v rb iv 0 0.6 - v v rt iv - 2.6 2.8 v internal bias v rb i 0.55 0.60 0.65 v v rt -v rb i 1.9 2.0 2.1 v short v rt and v rts short v rb and v rbs offset voltage error top i -18 -25 -68 mv bottom i 0 10 40 mv timing characteristics maximum conversion rate 1 mhz input sine wave i 20 30 msps output data delay (td) iv 18 30 ns output data delay (high z) iv 100 ns (tdish, tdisl) data valid time tri-state circuit iv 100 ns (teneh, tenel) sampling time offset iv 5 10 ns absolute maximum ratings (beyond which damage may occur) (1) 25 c supply voltages v dd ........................................................... -0.5 to +7.0 v input voltages analog input .............................................. agnd to v dd reference input voltage ........................... agnd to v dd esd susceptibility (2) ................................................. 1,500 v temperature operating temperature ................................. 0 to +70 c junction temperature ........................................... 175 c lead temperature, (soldering 10 seconds) .......... 300 c storage temperature ................................ -55 to +125 c notes: 1. operation at any absolute maximum rating is not implied. see electrical specifications for proper nominal applied conditions in typical applications. 2. 100 pf discharged through a 1.5 k w resistor (human body model). note: it is strongly recommended that all of the supply pins (av dd , dv dd ) be powered from the same source.
spt 3 6/24/97 SPT1175 electrical specifications t a =+25 c, av dd =dv dd =+5.0 v, agnd=dgnd=0.0 v, v rb =+0.6 v and v rt =+2.6 v, unless otherwise specified. test test SPT1175 parameters conditions level min typ max units dynamic performance signal-to-noise ratio f s = 20 msps f in =1.0 mhz i 44 46 db f in =3.58 mhz i 43 45 db f in =10 mhz v 39 db spurious free dynamic range f s = 20 msps f in =1.0 mhz i 44 47 db f in =3.58 mhz i 41 44 db f in =10 mhz v 33 db differential phase ntsc 20 ire mod ramp v 0.7 degrees differential gain f s = 14.3 msps v 1.0 % digital inputs input current, logic high v dd = 5.25 v, v ih = v dd i 1.0 m a input current, logic low v dd = 5.25 v, v il = dgnd i 1.0 m a pulse width high (clk) iv 15 ns pulse width low (clk) iv 15 ns voltage, logic high i 4.0 v voltage, logic low i 1.0 v digital outputs output current, high v dd = 4.75 v iv -1.1 ma output current, low v dd = 4.75 v iv 3.5 ma output current, high z v dd = 5.25 v, oe = v dd iv 16 m a voltage high i 4.0 v voltage low i 0.4 v power supply requirements analog supply voltage (av dd ) iv +4.75 +5.0 +5.25 v digital supply voltage (dv dd ) iv +4.75 +5.0 +5.25 v supply voltage difference (av dd -dv dd ) iv -0.1 0.0 0.1 v supply current f s =20 msps i 18 27 ma power dissipation i 90 135 mw test procedure 100% production tested at the specified temperature. 100% production tested at t a = +25 c, and sample tested at the specified temperatures. qa sample tested only at the specified temperatures. parameter is guaranteed (but not tested) by design and characterization data. parameter is a typical value for information purposes only. 100% production tested at t a = +25 c. parameter is guaranteed over specified temperature range. test level i ii iii iv v vi test level codes all electrical characteristics are subject to the following conditions: all parameters having min/max specifications are guar- anteed. the test level column indicates the specific device testing actually performed during production and quality assurance inspection. any blank section in the data column indicates that the specification is not tested at the specified condition.
spt 4 6/24/97 SPT1175 table i - output coding digital index analog input (v) output 0 0.6078125 00000000 1 0.6078125 ~ 0.6156260 00000001 v rb =0.6 v 2 0.6156250 ~ 0.6234375 00000010 v rt =2.6 v .... .... .... 123 1.5921875 ~ 1.6000000 01111111 1 lsb=7.8125 mv 124 1.6000000 ~ 1.6078125 10000000 125 1.6078125 ~ 1.6156250 10000001 .... .... .... 254 2.5843750 ~2.5921875 11111110 255 2.5921875 ~ 11111111 data (n-3) data (n-2) data (n-1) data (n) t d v in (n) v in (n+1) v in (n+2) v in (n+3) data clock v in figure 1a: timing diagram figure 1b: tri-state output timing diagram dut 2.5 v 220 w 50 pf 50% 2.5 v 90% tdisl 50% 2.5 v 90% tenel 10% v ol v ol 50% 2.5 v 10% tdish 50% 2.5 v 90% teneh v oh v oh oe oe oe oe
spt 5 6/24/97 SPT1175 typical interface circuit the SPT1175 is an 8-bit analog-to-digital converter which uses a two-step, ping-pong architecture to perform conver- sions up to 20 msps. figure 2 shows the typical interface requirements when using the SPT1175 in normal operation. the following sections describe the function and operation of the device. power supplies and grounding the SPT1175 operates from a single +5 v power supply. av dd and dv dd must be supplied from the same source (analog +5 v) to prevent a latch-up condition due to power supply sequencing. each power supply pin should be by- passed as closely as possible to the device. for optimal performance, both the agnd and dgnd should be con- nected to the system's analog ground plane. analog input and voltage reference the SPT1175 input voltage range is v rt >v in >v rb . two reference voltages (v rt and v rb ) are required for device operation. these voltages may be generated externally or the SPT1175's internal reference may be used. inside the SPT1175, reference resistors are placed between av dd and v rts and between agnd and v rbs so that v rts and v rbs generate the 2.6 v and 0.6 v references respec- tively. (see figure 3.) in order to utilize the internal self-bias reference voltage, v rts is to be shorted with v rt and the v rbs pin is to be shorted to the v rb pin. the self-bias internal reference is not as stable over temperature and supply variations as externally generated reference voltages but will perform well in many commercial video applications. figure 3 - reference circuit diagram SPT1175 2.6 v 0.6 v v rts v rt v rb v rbs agnd 0 v av dd 5.0v digital inputs and outputs the analog input is sampled and tracked on the first 'h' cycle of the external clock and is held from the falling edge of clk. the output remains valid (output hold time), and the new data becomes valid (output delay time) after the rising edge of clk, delayed by 2.5 clock cycles. the clock input and output enable input must be driven at cmos-compatible levels. evaluation board the eb1175 evaluation board is available to aid designers in demonstrating the full performance of the SPT1175. this board includes a reference circuit, clock driver circuit, output data latches, and an on-board reconstruction dac. an appli- cation note describing the operation of the board is available. contact the factory for price and delivery. figure 2 - typical interface circuit 2k r2 r10 dv dd av dd av dd v rts v rt av dd v in agnd agnd v rbs v rb dgnd clk dv dd d7 d6 d2 d1 dgnd d3 d4 d5 d0 +5 v 13 14 15 16 17 18 19 20 21 22 23 24 12 11 10(msb) 9 8 7 6 5 4 3 (lsb) 2 1 +5 v u1 + _ -15 +15 c28 c29 u2 + _ -15 +15 c61 c8 10 k 7.5 k r6 c58 2 3 -15 v in 2k +5 750 r1 r9 q1 4 7 75 r35 3 2 750 r36 r37 750 6 r15 10 c59 c60 -5 +5 750 r8 q2 r13 200 oe fb d1 d2 u1=eleantec, el2030 u2=op.07 d1=d2=rca, sk9091 q1=q2=2n2222a fr=fairrite, 274300 1111 all capacitors are 0.01 f unless otherwise specified. 3-st +5 en outputs +15 -15 gnd 10 10 10 + 10 +5 +15 -15 gnd + +5 + -5 -5 + note: av dd and dv dd must be supplied from the same source (analog +5 v) to prevent a latch-up condition due to power supply sequencing.
spt 6 6/24/97 SPT1175 package outlines 24-lead plastic dip 24-lead soic 1 24 a b cd e f g i h a b c d e 1 24 j f g h k i inches millimeters symbol min max min max a 0.130 0.230 3.30 5.84 b 0.115 0.200 2.92 5.08 c 0.014 0.023 0.36 0.58 d 0.045 0.070 1.14 1.78 e .100 typ 2.54 0.00 f 0.008 0.015 0.20 0.38 g 0.115 0.195 2.92 4.95 h .30 typ 7.62 0.00 i 0.240 0.310 6.10 7.87 j 1.180 1.285 29.97 32.64 k .005 typ 0.13 inches millimeters symbol min max min max a 0.587 0.606 14.90 15.40 b c .050 typ 1.27 typ d 0.014 0.022 0.35 0.55 e 0.006 0.012 0.15 0.30 f 0.067 0.089 1.70 2.25 g 0.012 0.028 0.30 0.70 h 0.295 0.327 7.50 8.30 i 0.205 0.220 5.20 5.60
spt 7 6/24/97 SPT1175 package outlines 28-lead plcc a b pin 1 c d e f g h top view pin 1 bottom view i inches millimeters symbol min max min max a 0.450 0.456 11.43 11.58 b 0.485 0.495 12.32 12.57 c45 45 d 0.165 0.175 4.19 4.45 e 0.010 0.25 f 0.022 typ .56 typ 0.00 g 0.18 typ 4.57 typ 0.00 h 0.05 typ 1.27 typ 0.00 i 0.039 0.430 0.99 10.92
spt 8 6/24/97 SPT1175 v rt 20 25 agnd n/c 22 21 av dd 19 v rts 11 d6 10 d5 9 d4 8 n/c 7 d3 6 d2 5 d1 26 27 28 1 4 2 3 v rbs v rb dgnd n/c dgnd d oe agnd 22 23 v in 17 av dd 16 dv d d 14 clk 13 dv dd 12 d7 15 n/c 18 av dd oe dgnd d (lsb) d1 d2 d3 d4 d5 d6 d7 (msb) dv dd clk dgnd v rb v rbs agnd agnd v in av dd v rt v rts av dd av dd dv dd pin assignments dip and soic plcc pin functions name function oe tri-state output enable tri-state when o e = dv dd , enable when o e = dgnd dgnd digital ground d0 digital output data (lsb) d1-6 digital output data d7 digital output data (msb) dv dd digital supply clk cmos digital clock input av dd analog supply v rts internal self-biased reference top shorted with v rt (pin 17). generates 2.6 v. v rt reference resistor top side v in analog input agnd analog ground v rbs internal self-biased reference bottom shorted with v rb (pin 23). generates 0.6 v. v rb reference resistor bottom side ordering information part number temperature range package type SPT1175acn 0 to +70 c 24l plastic dip SPT1175acp 0 to +70 c 28l plcc SPT1175acs 0 to +70 c 24l soic SPT1175acu +25 c die* *see the die specification for guaranteed electrical performance. signal processing technologies, inc. reserves the right to change products and specifications without notice. permission is her eby expressly granted to copy this literature for informational purposes only. copying this material for any other use is strictly prohibited . warning - life support applications policy - spt products should not be used within life support systems without the specific written consent of spt. a life support system is a product or system intended to support or sustain life which, if it fails, ca n be reasonably expected to result in significant personal injury or death. signal processing technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device failure. it is therefore not recommended, and exposure of a device to such a process will void the product warranty.
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